Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a rail-to-rail amplifier.
In general, a technology for a low voltage operation is desirable in a semiconductor technology. However, as an operation voltage is reduced, the swing range of a signal inputted to a semiconductor device is also narrowed. In this regard, many technologies have been developed to overcome concerns caused by the narrowed swing range of the input signal. A rail-to-rail amplifier is one of representative devices used for a low voltage operation.
In the rail-to-rail amplifier, differential input signals are applied to both a pair of NMOS transistors and a pair of PMOS transistors, unlike an operational amplifier in which differential input signals are applied to either a pair of NMOS transistors or a pair of PMOS transistors. The differential input signal may have all values in an allowable range of input voltages of the rail-to-rail amplifier in and around a common-mode voltage level. The common-mode voltage level represents a DC level at the crossing point of the differential input signals.
FIG. 1 is an internal configuration diagram of a conventional rail-to-rail amplifier.
Referring to FIG. 1, the rail-to-rail amplifier 100 includes an NMOS type amplification unit 110, a PMOS type folded-cascode amplification unit 120, and a biasing unit 130. The NMOS type amplification unit 110 receives differential input signals VIN and VINB and performs an amplification operation in a domain in which the DC levels of the differential input signals VIN and VINB are higher than a first threshold value V1. The PMOS type folded-cascode amplification unit 120 receives the differential input signals VIN and VINB and performs an amplification operation in a domain in which the DC levels of the differential input signals VIN and VINB are lower than a second threshold value V2 which is higher than the first threshold value V1. The PMOS type folded-cascode amplification unit 120 is cascade-coupled to the NMOS type amplification unit 110. The biasing unit 130 applies a first bias signal VBIAS1 and a second bias signal VBIAS2 to the PMOS type folded-cascode amplification unit 120. The NMOS type amplification unit 110 and the PMOS type folded-cascode amplification unit 120 may share one loading section A.
The operation of the conventional rail-to-rail amplifier 100 of FIG. 1 is described below. In the rail-to-rail amplifier 100, when the DC levels of the differential input signals VIN and VINB are lower than the first threshold value V1 in an allowable input voltage range of the rail-to-rail amplifier 100, only the PMOS type folded-cascode amplification unit 120 performs the amplification operation. When the DC levels of the differential input signals VIN and VINB are higher than the first threshold value V1 and lower than the second threshold value V2 in the allowable range of the rail-to-rail amplifier 100, both the NMOS type amplification unit 110 and the PMOS type folded-cascode amplification unit 120 perform the amplification operation. When the DC levels of the differential input signals VIN and VINB are higher than the second threshold value V2 in the allowable range of the rail-to-rail amplifier 100, only the NMOS type amplification unit 110 performs the amplification operation.
FIG. 2 is an internal configuration diagram of another conventional rail-to-rail amplifier.
The rail-to-rail amplifier 200 of FIG. 2 includes amplification units having an opposite type as compared with the rail-to-rail amplifier of FIG. 1.
Referring to FIG. 2, the rail-to-rail amplifier 200 includes a PMOS type amplification unit 210, an NMOS type folded-cascode amplification unit 220, and a biasing unit 230. The PMOS type amplification unit 210 receives differential input signals VIN and VINB and performs an amplification operation in a domain in which the DC levels of the differential input signals VIN and VINB are lower than a first threshold value V1. The NMOS type folded-cascode amplification unit 220 receives the differential input signals VIN and VINB and performs an amplification operation in a domain in which the DC levels of the differential input signals VIN and VINB are higher than a second threshold value V2 which is lower than the first threshold value V1. The NMOS type folded-cascode amplification unit 220 is cascade-coupled to the PMOS type amplification unit 210. The biasing unit 230 applies a first bias signal VBIAS1 and a second bias signal VBIAS2 to the NMOS type folded-cascode amplification unit 220. The PMOS type amplification unit 210 and the NMOS type folded-cascode amplification unit 220 may share one loading section B.
The operation of the conventional rail-to-rail amplifier 200 of FIG. 2 is described below.
In the rail-to-rail amplifier 200, when the DC levels of the differential input signals VIN and VINB are equal to or less than the second threshold value V2, only the PMOS type amplification unit 210 performs the amplification operation. When the DC levels of the differential input signals VIN and VINB are between the first threshold value V1 and the second threshold value V2, both the PMOS type amplification unit 210 and the NMOS type folded-cascode amplification unit 220 perform the amplification operation. When the DC levels of the differential input signals VIN and VINB are equal to or more than the first threshold value V1, for example, only the NMOS type folded-cascode amplification unit 220 performs the amplification operation.
However, the above-described rail-to-rail amplifiers 100 and 200 have the following concerns.
FIG. 3 is a graph illustrating the current-voltage characteristics and the voltage gain of the rail-to-rail amplifier 100 of FIG. 1 according to the DC levels of the differential input signals, and FIG. 4 is a graph illustrating the current-voltage characteristics and the voltage gain of the rail-to-rail amplifier 200 of FIG. 2 according to the DC levels of the differential input signals.
Referring to FIG. 3, a constant amount of bias current 2xICAS flows through a sinking section N4 and N5 of the PMOS type folded-cascode amplification unit 120 regardless of the DC levels of the differential input signals VIN and VINB. This is because the second bias signal VBIAS2 applied to the sinking section N4 and N5 is constant. Consequently, since the bias current 2xICAS flowing through the sinking section N4 and N5 maintains a constant value regardless of the differential input signals VIN and VINB, it can be understood that a bias current 2xILOAD of a common loading section A and a bias current ICS_P of a sourcing section P3 included in the PMOS type folded-cascode amplification unit 120 are complementary to each other. That is, a reduction in one of the bias current 2xILOAD and the bias current ICS_P causes an increase in the other one thereof (2xICAS=2xILOAD+ICS_P).
When the DC levels of the differential input signals VIN and VINB are equal to or less than the first threshold value V1, the amount of the bias current 2xILOAD flowing through the common loading section A has a tendency to be constant. Thus, since an output resistance of the common loading section A is constantly maintained, the voltage gain Av of the rail-to-rail amplifier 100 is constantly maintained. Meanwhile, when the DC levels of the differential input signals VIN and VINB are equal to or more than the first threshold value V1, the amount of the bias current 2xILOAD flowing through the common loading section A has a tendency to be increased. This is because the first bias signal VBIAS1 and the second bias signal VBIAS2 are constantly applied to the PMOS type folded-cascade amplification unit 120, and the sourcing section P3 and the sinking section N4 and N5 continue to be in an enabled state regardless of the differential input signals VIN and VINB. Thus, the output resistance of the common loading section A is gradually reduced, resulting in the reduction in the voltage gain Av of the rail-to-rail amplifier 100. Meanwhile, when the DC levels of the differential input signals VIN and VINB are equal to or more than the second threshold value V2, only the NMOS type amplification unit 110 performs the amplification operation. In such a case, the voltage gain Av of the rail-to-rail amplifier 100 is minimized. That is, when the NMOS type amplification unit 110 performs the amplification operation according to the DC levels of the differential input signals VIN and VINB, an unnecessary current path P1 may be formed (see FIG. 1), resulting in a negative influence on the voltage gain Av of the rail-to-rail amplifier 100.
Referring to FIG. 4, when the rail-to-rail amplifier 200 of FIG. 2 performs the amplification operation, the amount of the bias current 2xICAS flowing through a second sourcing section P14 and P15 is the same as the sum of a bias current ICS_N flowing through a first sinking section N15 and a bias current 2xILOAD flowing through a common loading section B (2xICAS=ICS_N+2xILOAD).
When the DC levels of the differential input signals VIN and VINB are equal to or less than the first threshold value V1, the amount of the bias current 2xILOAD flowing through the common loading section B may be higher than a desired current amount. This is because the second sourcing section P14 and P15 continue to be enabled by the second bias signal VBIAS2 regardless of the differential input signals VIN and VINB, and an unnecessary current is introduced to the common loading section B. In other words, an unnecessary current path P2 may be formed when the PMOS type amplification unit 210 performs the amplification operation (see FIG. 2), resulting in the reduction in the voltage gain Av of the rail-to-rail amplifier 200.